1. Field of the Invention
The present invention relates to a request arbitration device such as a bus arbiter for arbitrating requests of access etc. to a predetermined memory from a plurality of initiators, and a memory controller.
2. Description of the Background Art
FIG. 15 is a block diagram showing a system configuration of a bus arbiter of the prior art and peripheral parts thereof. As shown in the figure, a bus arbiter 64 is arranged between a CPU 60 and initiators 61 to 63, and a SDRAM memory controller 65.
The bus arbiter 64 arbitrates requests from the CPU 60 and the initiators 61 to 63, and issues a request to the SDRAM memory controller 65. Each initiator 61 to 63 requires an image system (3D, 3D) and image compression, and transfer of great amount of data such as voice, and the like. The bus arbiter 64 thus needs to perform arbitration to satisfy the request from each initiator 61 to 63.
A request on different addresses in an SDRAM (Synchronous Dynamic Random Access Memory) 66 is issued from each initiator 61 to 63 to the bus arbiter 64. It becomes necessary to enhance a command issuing efficiency on the SDRAM 66 by performing arbitration in the bus arbiter 64 such that penalty due to page miss, bank miss, and interruption by another initiator in time of access of the SDRAM 64 reduces. The penalty includes bank miss penalty, page miss penalty, and the like.
In order to enhance the command issue efficiency on the SDRAM 66, arbitration taking bank hit/miss of the SDRAM 66, preceding PRE, ACT command issue to the SDRAM 66, and the like into consideration is performed in the bus arbiter 64.
An arbitration technique of memory access request with enhanced command issue efficiency on the SDRAM 66 includes a technique disclosed in Unexamined Japanese Patent Application Laid-Open No. 2006-99199 and the like. In Unexamined Japanese Patent Application Laid-Open No. 2006-99199, an arbitration technique of preferentially giving access permission to a memory master requesting an access to the same page as the last access page is disclosed.
FIG. 16 is a block diagram showing the SDRAM memory controller 65 and the peripherals thereof. An access efficiency enhancing method of an eight-bank SDRAM is generally adopted in the SDRAM memory controller 65.
The SDRAM memory controller 65 issues a command to the SDRAM 66 in response to a request from the bus arbiter 64.
In the SDRAM including DDR2 (Double-Dta-Rate2)-SDRAM and the like, the SDRAM of four, eight bank articles exists. When using eight bank articles, the eight-bank article control method opens up to four banks in the SDRAM memory controller, and the bank to be closed when opening the fifth bank is a determined bank that forms a pair.
A waiting time during which the processing data of each initiator does not break needs to be taken into consideration in the bus arbiter. The waiting time during which the initiator does not break is referred to as “permissible time”. The data breakage of the initiator refers to disturbance of image in the initiator of graphics system, interruption of voice in the initiator of voice system, and the like.
However, in the conventional bus arbiter or the technique of arbitrating the memory access request disclosed in Unexamined Japanese Patent Application Laid-Open No. 2006-99199, request arbitration that takes the permissible time into consideration is not performed.
In addition to not taking the permissible time into consideration, in the eight bank article control method, the bank that is likely to be accessed might get closed since the bank to be closed when opening the fifth bank is the determined bank that forms a pair. The SDRAM access performance thus might lower.